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ks8997/KSZ8997 8-port 10/100 integrated switch with phy and frame buffer rev 1.1 micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? te l +1 (408) 944-0800 ? fax + 1 (408) 474-1000 ? http://www.micre l.com february 2007 m9999-022807-1.31 general description the ks8997 contains eight 10/100 physical layer transceivers, eight mac (medi a access control) units with an integrated layer 2 switch. the device runs as an eight port integrated switch. the ks8997 is designed to reside in an unmanaged design not requiring processor intervention. this is achieved through i/o strapping or eeprom programming at system reset time. on the media side, the ks8997 supports 10baset and 100basetx through auto-negotiation as specified by the ieee 802.3 committee. physical signal transmission and reception are enhanced through use of analog circuitry that makes the design more efficient and allows for lower power consumption and smaller chip die size. data sheets and support documentation can be found on micrel?s web site at www.micrel.com. functional diagram
micrel, inc. ks8997/KSZ8997 february 2007 2 m9999-022807-1.1 features ? 8-port 10/100 integrated switch with 8 physical layer transceivers ? 32kx32 of sram on chip for frame buffering ? 2.0gbps high performance memory bandwidth ? 10baset and 100basetx modes of operation ? superior analog technology for reduced power and die size ? single 2.0v power supply with options for 2.5v and 3.3v i/o ? 900ma (1.80 w) including physical transmit drivers ? supports port based vlan ? supports diffserv priority, 802.1p based priority or port based priority ? indicators for link, activity, full/half-duplex and speed ? unmanaged operation via st rapping or eeprom at system reset time ? hardware based 10/100, full/half, flow control and auto negotiation ? wire speed reception and transmission ? integrated address look-up engine, supports 1k absolute mac addresses ? automatic address learning, address aging and address migration ? broadcast storm protection ? full-duplex ieee 802.3x flow control ? half-duplex back pres sure flow control ? comprehensive led support ? supports mdi/mdi-x auto crossover ? commercial temperature range: 0c to +70c ? supports lead free product (KSZ8997) for commercial temperature range: 0c to +70c ? available in 128-pin pqfp package applications ? small workgroup switches ? voip infrastructure switches ordering information part number temp. range package ks8997 0c to +70c 128-pin pqfp KSZ8997 0c to +70c 128-pin pqfp
micrel, inc. ks8997/KSZ8997 february 2007 3 m9999-022807-1.1 revision history revision date summary of changes 1.00 11/27/00 document origination. 1.01 04/02/01 update maximum frame size. update eeprom priority descriptions. update i/o descriptions. update electrical characteristics. 1.02 05/11/01 add mdi/m di_x description/ 1.03 06/22/01 change electrical requirements. 1.04 06/25/01 correct i/o descriptions. 1.05 07/25/01 update pll clock information. 1.06 05/29/02 correct led[1: 8][3] mode 2 description. 1.07 08/29/03 convert to new format. 1.1 02/27/07 added lead free commercial temperature package.
micrel, inc. ks8997/KSZ8997 february 2007 4 m9999-022807-1.1 contents system level applicat ions ...................................................................................................... ..........................................6 pin descri ption ................................................................................................................ ..................................................7 i/o gr ouping ................................................................................................................... .................................................11 i/o descriptions............................................................................................................... ................................................11 pin config uration.............................................................................................................. ...............................................14 functional overview: phys ical layer transceiver ................................................................................ ..........................15 100basetx tr ansmit............................................................................................................. ......................................15 100basetx re ceive.............................................................................................................. ......................................15 pll clock synthesizer .......................................................................................................... ......................................15 scrambler/de-scrambler (100basetx only)........................................................................................ .......................15 10baset transmit ............................................................................................................... ........................................15 10baset receive ................................................................................................................ ........................................15 power mana gement ............................................................................................................... .....................................15 power save mode ............................................................................................................................... ...............15 mdi/mdi-x auto crossover....................................................................................................... ..................................16 auto-negot iation............................................................................................................... ...........................................16 functional overview : switch core ............................................................................................... ...................................17 address look-up................................................................................................................ .........................................17 learning....................................................................................................................... ................................................17 migration...................................................................................................................... ................................................17 aging .......................................................................................................................... .................................................17 forwarding..................................................................................................................... ..............................................17 switching engine............................................................................................................... ..........................................17 mac (media access c ontroller) op eration ........................................................................................ .........................18 inter-packet gap (ipg) ............................................................................................................................... .......18 backoff algorithm ............................................................................................................................... ................18 late collision ............................................................................................................................... .......................18 illegal frames ............................................................................................................................... ......................18 flow control ............................................................................................................................... ........................18 half-duplex ba ck pressure ............................................................................................................................... .18 broadcast storm protection ............................................................................................................................... 18 programmable featur es .......................................................................................................... .......................................19 priority schemes ............................................................................................................... ..........................................19 per port met hod ................................................................................................................ ..........................................19 802.1p me thod .................................................................................................................. ..........................................19 ipv4 dscp method ............................................................................................................... ......................................19 other priority considerations .................................................................................................. ....................................19 vlan oper ation ................................................................................................................. .............................................20 station mac address (con trol frames only) ...................................................................................... ..............................21 eeprom oper ation ............................................................................................................... .........................................21 eeprom memo ry map.............................................................................................................. .................................21 general contro l register....................................................................................................... ......................................21
micrel, inc. ks8997/KSZ8997 february 2007 5 m9999-022807-1.1 priority classification c ontrol ? 802.1p tag field............................................................................. .............................21 port 1 contro l register........................................................................................................ ........................................22 port 2 contro l register........................................................................................................ ........................................22 port 3 contro l register........................................................................................................ ........................................22 port 4 contro l register........................................................................................................ ........................................23 port 5 contro l register........................................................................................................ ........................................23 port 6 contro l register........................................................................................................ ........................................23 port 7 contro l register........................................................................................................ ........................................24 port 8 contro l register........................................................................................................ ........................................24 reserved register.............................................................................................................. .........................................25 port 1 vlan ma sk register ...................................................................................................... ..................................25 port 2 vlan ma sk register ...................................................................................................... ..................................25 port 3 vlan ma sk register ...................................................................................................... ..................................26 port 4 vlan ma sk register ...................................................................................................... ..................................26 port 5 vlan ma sk register ...................................................................................................... ..................................26 port 6 vlan ma sk register ...................................................................................................... ..................................27 port 7 vlan ma sk register ...................................................................................................... ..................................27 port & vlan ma sk register ...................................................................................................... ..................................28 reserved register.............................................................................................................. .........................................28 port 1 vlan tag insert ion value r egisters...................................................................................... ..........................28 port 2 vlan tag insert ion value r egisters...................................................................................... ..........................28 port 3 vlan tag insert ion value r egisters...................................................................................... ..........................28 port 4 vlan tag insert ion value r egisters...................................................................................... ..........................29 port 5 vlan tag insert ion value r egisters...................................................................................... ..........................29 port 6 vlan tag insert ion value r egisters...................................................................................... ..........................29 port 7 vlan tag insert ion value r egisters...................................................................................... ..........................29 port 8 vlan tag insert ion value r egisters...................................................................................... ..........................29 reserved register.............................................................................................................. .........................................29 diff serv code po int registers................................................................................................. ...................................29 station mac address registers (all po rts ? mac control frames only) ............................................................ ..........30 absolute maxi mum ratings ....................................................................................................... .....................................31 operating ratings .............................................................................................................. .............................................31 electrical char acteristics ..................................................................................................... ............................................31 timing di agrams ................................................................................................................ .............................................33 reference circuit.............................................................................................................. ...............................................34 4b/5b coding ................................................................................................................... ...............................................35 mlt3 coding.................................................................................................................... ...............................................36 mac frame fo r 802.3............................................................................................................ ..........................................36 selection of isol ation transformer ............................................................................................. .....................................37 selection of referenc e oscillator /crystal...................................................................................... ..................................37 package info rmation ............................................................................................................ ...........................................38
micrel, inc. ks8997/KSZ8997 february 2007 6 m9999-022807-1.1 system level applications the ks8997 can be configured to fit in an eight port 10/100 application. the majo r benefits of using the ks8997 are the lower power consumption, unmanaged operation, flexible configuration, built in frame buffering, vlan abilities and traffic priority control. an application is depicted below.
micrel, inc. ks8997/KSZ8997 february 2007 7 m9999-022807-1.1 pin description pin number pin name type(1) port pin function 1 vdd_rx pwr 2.0v for equalizer 2 gnd_rx gnd ground for equalizer 3 gnd_rx gnd ground for equalizer 4 vdd_rx pwr 2.0v for equalizer 5 rxp[3] i 3 physical receive signal + (differential) 6 rxm[3] i 3 physical receive signal ? (differential) 7 gnd-iso gnd analog ground 8 txp[3] o 3 physical transmit signal + (differential) 9 txm[3] o 3 physical transmit signal ? (differential) 10 gnd_tx gnd ground for transmit circuitry 11 vdd_tx pwr 2.0v for transmit circuitry 12 txp[4] o 4 physical receive signal + (differential) 13 txm[4] o 4 physical receive signal ? (differential) 14 gnd_tx gnd ground for transmit circuitry 15 rxp[4] i 4 physical receive signal + (differential) 16 rxm[4] i 4 physical receive signal ? (differential) 17 gnd_rx gnd ground for equalizer 18 vdd_rx pwr 2.0v for equalizer 19 iset set physical transmit output current 20 gnd-iso gnd analog ground 21 vdd_rx pwr 2.0v for equalizer 22 gnd_rx gnd ground for equalizer 23 rxp[5] i 5 physical receive signal + (differential) 24 rxm[5] i 5 physical receive signal ? (differential) 25 gnd_tx gnd ground for transmit circuitry 26 txp[5] o 5 physical receive signal + (differential) 27 txm[5] o 5 physical receive signal ? (differential) 28 vdd_tx pwr 2.0v for transmit circuitry 29 gnd_tx gnd ground for transmit circuitry 30 txp[6] o 6 physical receive signal + (differential) 31 txm[6] o 6 physical receive signal ? (differential) 32 gnd-iso gnd analog ground 33 rxp[6] i 6 physical receive signal + (differential) 34 rxm[6] i 6 physical receive signal ? (differential) 35 vdd_rx pwr 2.0v for equalizer 36 gnd_rx gnd ground for equalizer 37 gnd_rx gnd ground for equalizer 38 vdd_rx pwr 2.0v for equalizer
micrel, inc. ks8997/KSZ8997 february 2007 8 m9999-022807-1.1 pin number pin name type(1) port pin function 39 gnd-iso gnd analog ground 40 rxp[7] i 7 physical receive signal + (differential) 41 rxm[7] i 7 physical receive signal - (differential) 42 gnd_tx gnd ground for transmit circuitry 43 txp[7] o 7 physical receive signal + (differential) 44 txm[7] o 7 physical receive signal - (differential) 45 vdd_tx pwr 2.0v for transmit circuitry 46 vdd_tx pwr 2.0v for transmit circuitry 47 txp[8] o 8 physical receive signal + (differential) 48 txm[8] o 8 physical receive signal - (differential) 49 gnd_tx gnd ground for transmit circuitry 50 rxp[8] i 8 physical receive signal + (differential) 51 rxm[8] i 8 physical receive signal - (differential) 52 gnd_rx gnd ground for equalizer 53 vdd_rx pwr 2.0v for equalizer 54 gnd_rcv gnd ground for clock recovery circuit 55 vdd_rcv pwr 2.0v for clock recovery circuit 56 gnd_rcv gnd ground for clock recovery circuit 57 vdd_rcv pwr 2.0v for clock recovery circuit 58 rlpbk i enable loop back for testing 59 t[1] i factory test pin ? float for normal operation 60 en1p i enable 802.1p for all ports 61 sda i/o serial data from eeprom or processor 62 scl i/o clock for eeprom or from processor 63 vdd pwr 2.0v for core digital circuitry 64 gnd gnd ground for core digital circuitry 65 vdd-io pwr 2.0v, 2.5v or 3.3v for i/o circuitry 66 gnd gnd ground for digital circuitry 67 gnd gnd ground for core digital circuitry 68 vdd pwr 2.0v for core digital circuitry 69 bist i built-in self test?tie low for normal operation 70 rst# i reset 71 led[1][3] i/o 1 led indicator 3 72 led[1][2] i/o 1 led indicator 2 73 led[1][0] i/o 1 led indicator 0 74 led[2][3] i/o 2 led indicator 3 75 led[2][2] i/o 2 led indicator 2 76 led[2][0] i/o 2 led indicator 0 77 vdd-io pwr 2.0v, 2.5v or 3.3v for i/o circuitry
micrel, inc. ks8997/KSZ8997 february 2007 9 m9999-022807-1.1 pin number pin name type(1) port pin function 78 gnd gnd ground for digital circuitry 79 led[3][3] i/o 3 led indicator 3 80 led[3][2] i/o 3 led indicator 2 81 led[3][0] i/o 3 led indicator 0 82 led[4][3] i/o 4 led indicator 3 83 led[4][2] i/o 4 led indicator 2 84 led[4][0] i/o 4 led indicator 0 85 vdd pwr 2.0v for core digital circuitry 86 gnd gnd ground for core digital circuitry 87 led[5][3] i/o 5 led indicator 3 88 led[5][2] i/o 5 led indicator 2 89 led[5][0] i/o 5 led indicator 0 90 led[6][3] i/o 6 led indicator 3 91 led[6][2] i/o 6 led indicator 2 92 led[6][0] i/o 6 led indicator 0 93 led[7][3] i/o 7 led indicator 3 94 led[7][2] i/o 7 led indicator 2 95 vdd-io pwr 2.0v, 2.5v or 3.3v for i/o circuitry 96 led[7][0] i/o 7 led indicator 0 97 led[8][3] i/o 8 led indicator 3 98 led[8][2] i/o 8 led indicator 2 99 led[8][0] i/o 8 led indicator 0 100 gnd gnd ground for digital circuitry 101 gnd gnd ground for core digital circuitry 102 vdd pwr 2.0v for core digital circuitry 103 modesel[1] i selects led modes 104 modesel[0] i selects led modes 105 t[5] i factory test pin ? float for normal operation 106 x1 i crystal or clock input 107 x2 o connect to crystal 108 vdd_plltx pwr 2.0v for phase locked loop circuit 109 gnd_plltx gnd ground for phase locked loop circuit 110 vdd_rcv pwr 2.0v for clock recovery circuit 111 gnd_rcv gnd ground for clock recovery circuit 112 vdd_rcv pwr 2.0v for clock recovery circuit 113 gnd_rcv gnd ground for clock recovery circuit 114 vdd_rx pwr 2.0v for equalizer 115 gnd_rx gnd ground for equalizer 116 rxp[1] i 1 physical receive signal + (differential)
micrel, inc. ks8997/KSZ8997 february 2007 10 m9999-022807-1.1 pin number pin name type(1) port pin function 117 rxm[1] i 1 physical receive signal ? (differential) 118 gnd_tx gnd ground for transmit circuitry 119 txp[1] o 1 physical transm it signal + (differential) 120 txm[1] o 1 physical transm it signal - (differential) 121 vdd_tx pwr 2.0v for transmit circuitry 122 vdd_tx pwr 2.0v for transmit circuitry 123 txp[2] o 2 physical transm it signal + (differential) 124 txm[2] o 2 physical transm it signal - (differential) 125 gnd_tx gnd ground for transmit circuitry 126 rxp[2] i 2 physical transm it signal + (differential) 127 rxm[2] i 2 physical transm it signal - (differential) 128 gnd-iso gnd analog ground notes: 1. pwr = power supply i = input o = output i/o = bi-directional gnd = ground
micrel, inc. ks8997/KSZ8997 february 2007 11 m9999-022807-1.1 i/o grouping group name description phy physical interface ind led indicators up unmanaged programmable ctrl control and miscellaneous test test (factory) pwr/gnd power and ground i/o descriptions group i/o names active status description phy rxp[1:8] rxm[1:8] analog differential inputs (receive) for connection to media transformer. txp[1:8] txm[1:8] analog differential outputs (transmit) for connection to media transformer. iset analog transmit current set. connect an exte rnal reference resistor to set transmitter output current. this pin is connected to a 1% 3k ? ? resistor to ground if a transformer with 1:1 turn ratio is used. led[1:8][0] l output (after reset) mode 0: speed (on = 100/off = 10) mode 1: reserve mode 2: collision (on = collision/off = no collision) mode 3: speed (on = 100/off = 10) led[1:8][2] l output (after reset) mode 0: collision (on = collision/off = no collision) mode 1: reserve mode 2: link activity (10mb mode) mode 3: full duplex + collision (constant on = full-duplex; int ermittent on = collision; off = half-duplex with no collision) ind led[1:8][3] l output (after reset) mode 0: link + activity mode 1: reserve mode 2: link activity (100mb mode) mode 3: link + activity note: mode is set by modesel[1:0] ; see description in up (unmanaged programming) section h mode select at reset time. led mode is selected by using the table below. modesel [1] [0] operation modesel[1:0] 0 0 1 1 0 1 0 1 led mode 0 led mode 1 led mode 2 led mode 3 led[1][3] reserved ? use float configuration led[1][2] reserved ? use float configuration led[1][0] reserved ? use float configuration led[2][3] reserved ? use float configuration up led[2][2] reserved ? use float configuration
micrel, inc. ks8997/KSZ8997 february 2007 12 m9999-022807-1.1 group i/o names active status description led[2][0] reserved ? use float configuration led[3][3] reserved ? use float configuration led[3][2] reserved ? use float configuration led[3][0] reserved ? use float configuration led[4][3] reserved ? use float configuration led[4][2] reserved ? use float configuration led[4][0] reserved ? use float configuration led[5][3] reserved ? use float configuration led[5][2] reserved ? use float configuration led[5][0] reserved ? use float configuration led[6][3] programs back-off aggressiveness for half-duplex mode. d = less aggressive back-off f/u = more aggressive back-off (default led[6][2] programs retries for frames that encounter collisions. led[6][0] reserved ? use float configuration led[7][3] programs flow control. d = no flow control f/u = flow control enabled (default) led[7][2] programs broadcast storm protection. d = 5% broadcast frames allowed f/u = unlimited broadcast frames (default) led[7][0] reserved ? use float configuration led[8][3] programs address aging. d = aging disabled f/u = enable 5 minute aging (default) led[8][2] programs frame length enforcement. d = max length for vlan is 1522 bytes and without vlan is 1518 bytes f/u = max length is 1536 bytes (default) led[8][0] programs half-duplex back pressure. d = no half-duplex back pressure f/u = half-suplex back pressure enabled (default) en1p h enable 802.1p for all ports: this enab les qos based on the priority field in the layer 2 header. 0 = 802.1p selected by port in eeprom 1 = use 802.1p priority field unless disabled in eeprom note: this is also controlled by the eeprom registers (registers 4-11 bit 4). the values in the eeprom supercede this pi n. also, if the priority selection is unaltered in the eeprom registers (register 3 bits 0-7) then values of ?100? and above are considered high priority a nd values of ?011? and below are low priority. x1 clock external crystal or clock input x2 clock used when other polarity of crystal is needed. this is unused for a normal clock input. scl clock clock for eeprom. sda serial data for eeprom. ctrl rst# l system reset. test t[1], t[5] factory test inputs: leave open (float) for normal operation rlpbk h factory test input: tie low for normal operation
micrel, inc. ks8997/KSZ8997 february 2007 13 m9999-022807-1.1 group i/o names active status description bist h factory test input: tie low for normal operation pwr/gnd vdd_rx 2.0v for equalizer gnd_rx ground for equalizer vdd_tx 2.0v for transmit circuitry gnd_tx ground for transmit circuitry vdd_rcv 2.0v for clock recovery circuitry gnd_rcv ground for clock recovery vdd_plltx 2.0v for phase locked loop circuitry gnd_plltx ground for phase locked loop circuitry gnd-sio analog ground vdd 2.0v for core digital circuitry vdd-io 2.0v, 2.5v or 3.3v digital for i/o circuitry gnd ground for digital circuitry note: 1. all unmanaged programming takes place at reset time only. for unmanaged programming: f = float, d = pull-down, u = pull-up, h = hold pin state after reset. se e ?reference circuits? section.
micrel, inc. ks8997/KSZ8997 february 2007 14 m9999-022807-1.1 pin configuration 128-pin pqfp (q)
micrel, inc. ks8997/KSZ8997 february 2007 15 m9999-022807-1.1 functional overview: phys ical layer transceiver 100basetx transmit the 100basetx transmit function performs parallel-to-ser ial conversion, 4b/5b coding, scrambling, nrz to nrzi conversion, mlt3 encoding and transmission. the circuit starts with a parallel to serial conversion, which converts the mii data from the mac into a 125mhz serial bit stream . the data and control stream is then converted into 4b/5b coding followed by a scrambler. the serialized data is further converted from nrz to nr zi format, and then transmitted in mlt3 current output. the output current is set by an external 1% 3.01k ? resistor for the 1:1 transformer ratio. it has a typical rise/fall time of 4ns and complies with the ansi tp-pmd standard rega rding amplitude balance, overshoot and timing jitter. the wave-shaped 10baset output is also incorp orated into the 100basetx transmitter. 100basetx receive the 100basetx receiver function performs adaptive equalizat ion, dc restoration, mlt3 to nrzi conversion, data and clock recovery, nrzi to nrz conversion, de-scrambling, 4b/5b decoding and serial to parallel conversion. the receiving side starts with the equalizati on filter to compensate for inter-symbol interference (isi) over the twisted pair cable. since the amplitude loss and phase distortion is a f unction of the length of the cable, the equalizer has to adjust its characteristics to optimize th e performance. in this design, the variable equalizer will make an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, then it tunes itself for optimization. this is an ongoing process and can self adjust against environmental changes such as temperature variations. the equalized signal then goes through a dc restoration and data conversion block. the dc restoration circuit is used to compensate for the effect of base line wander and improve the dynamic range. the differential data conversion circuit converts the mlt3 format back to nrzi. the slicing threshold is also adaptive. the clock recovery circuit extracts the 125mhz clock from the edges of the nrzi signal. this recovered clock is then used to convert the nrzi signal into the nrz format. the signal is then sent through the de-scrambler followed by the 4b/5b decoder. finally, the nrz serial data is converted to the m ii format and provided as the input data to the mac. pll clock synthesizer the ks8997 generates 125mhz, 62mhz, 25mhz and 10mhz clocks for system timing. internal clocks are generated from an external 25mhz crystal. scrambler/de-scrambler (100basetx only) the purpose of the scrambler is to spread the power spec trum of the signal in order to reduce emi and baseline wander. the data is scrambled through the use of an 11-bi t wide linear feedback shift register (lfsr). this can generate a 2047-bit non-r epetitive sequence. the receiver will then de-scramble the inco ming data stream with the same sequence at the transmitter. 10baset transmit the output 10baset driver is incorporat ed into the 100baset driver to allow transmission with the same magnetics. they are internally wave-shaped and pre-emphasize d into outputs with a typical 2.3v amplitude. 10baset receive on the receive side, input buffer and level detecting squelch circuits are employed. a differential input receiver circuit and a pll perform the decoding function. the manchester-encoded data stream is separated into clock signal and nrz data. a squelch circuit rejects signals with levels less than 400mv or with short pulse widths in order to prevent noises at the rxp or rxm input from falsely triggering t he decoder. when the input exceeds the squelch limit, the pll locks onto the incoming signal and the ks8997 decodes a data frame. the receiver clock is maintained active during idle periods in between data reception. power management power-save mode the ks8997 will turn off everything except for the energy dete ct and pll circuits when the cable is not installed on an individual port basis. in other words, the ks8997 will sh utdown most of the internal ci rcuits to save power if there is no link.
micrel, inc. ks8997/KSZ8997 february 2007 16 m9999-022807-1.1 mdi/mdi-x auto crossover the ks8997 supports mdi/mdi-x auto crosso ver. this facilitates t he use of either a strai ght connection cat-5 cable or a crossover cat-5 cable. the auto-sense function will detect remote transmit and receiv e pairs, and correctly assign the transmit and receive pairs from the micrel dev ice. this can be highly useful when end users are unaware of cable types and can also save on an addi tional uplink configuration connection. the auto mdi/mdi-x is achieved by the mi crel device listening for the far end transmission channel and assigning transmit/receive pairs accordingly. auto-negotiation the ks8997 conforms to the auto-negotiat ion protocol as described by the 80 2.3 committee. auto-negotiation allows utp (unshielded twisted pair) link partners to select t he best common mode of operati on. in auto-negotiation the link partners advertise capabilitie s across the link to each othe r. if auto-negotiation is not supported or the link partner to the ks8997 is forced to bypass auto- negotiation, then the mode is set by obser ving the signal at the receiver. this is known as parallel mode because while the transmitter is sending auto-negotiation adverti sements, the receiver is listening for advertisements or a fixed signal protocol. the flow for the link set up is depicted below. note that the ks8997 only supports auto-negotiation and not forced modes. figure 4. auto-negotiation
micrel, inc. ks8997/KSZ8997 february 2007 17 m9999-022807-1.1 functional overview: switch core address look-up the internal look-up table stores mac addresses and their associated informatio n. it contains 1k full cam with 48-bit address plus switching information. th e ks8997 is guaranteed to learn 1k addr esses and distinguishes itself from hash-based lookup tables wh ich, depending on the oper ating environment and probabilit ies, may not guarantee the absolute number of addresses it can learn. learning the internal look-up engine will update its table with a new entry if the following conditions are met: ? the received packet?s sa (source address) does not exist in the look-up table. ? the received packet is good; the packet has no receiving errors, and is of legal length. the look-up engine will insert the qualified sa into the table, along with the port number, time stamp. if the table is full, the last entry of the table will be deleted first to ma ke room for the new entry. migration the internal look-up engine also monitors whether a stat ion is moved. if it happens, it will update the table accordingly. migration happens when the following conditions are met: ? the received packet?s sa is in the table but the associated source port information is different. ? the received packet is good; the packet has no receiving errors, and is of legal length. the look-up engine will updat e the existing record in the table with the new so urce port information. aging the look-up engine will update time stamp information of a record wh enever the correspo nding sa appears. the time stamp is used in the aging process. if a record is not updated for a period of time, t he look-up engine will then remove the record from th e table. the look-up engine constantly performs the aging process an d will continuously remove aging records. the aging period is 300 seconds. th is feature can be enabled or disabled by external pull-up or pull-down resistors. forwarding the ks8997 will forward packets as follows: ? if the da look-up result is a ?match?, the ks8997 will use the destination port info rmation to determine where the packet goes. ? if the da look-up result is a ?miss?, the ks8997 will forw ard the packet to all other ports except the port that received the packet. ? all the multicast and bro adcast packets will be forw arded to all other ports except the source port. the ks8997 will not forward the following packets: ? error packets. these include framing errors, fcs erro rs, alignment errors, and illegal size packet errors. ? 802.3x pause frames. the ks8997 will intercept these packets an d do the appropriate actions. ? ?local? packets. based on destination address (da) look-u p. if the destination port from the look-up table matches the port where the packet was from, the packet is defined as ?local?. switching engine the ks8997 has a very high performance switching engine to move data to and from the mac?s, packet buffers. it operates in store and forward mode, while the effici ent switching mechanism reduces overall latency. the ks8997 has an internal buffer for frames that is 32kx32 (128kb). this resource could be shared between the nine ports and is programmed at system reset time by using the unmanaged program mode (i/o strapping). each buffer is sized at 128b and therefore there are a to tal of 1024 buffers available. the buffers are adaptively allocated up to 512 to a single port based on loading.
micrel, inc. ks8997/KSZ8997 february 2007 18 m9999-022807-1.1 mac (media access controller) operation the ks8995x strictly abides by ieee 802.3 standards to maximize compatibility. inter-packet gap (ipg) if a frame is successfully transmitted, the 96 bit time ipg is measured betw een the two consecutive mtxen. if the current packet is experiencing collision, the 96 bit ti me ipg is measured from mcrs and the next mtxen. backoff algorithm the ks8997 implements the ieee std 802. 3 binary exponential back-off algori thm, and optional ?a ggressive mode? back off. after 16 collisions, the packet will be optionally dr opped depending on the chip confi guration in register 3. see ?register 3.? late collision if a transmit packet experiences collisions after 512-bit times of the transmission, the pac ket will be dropped. illegal frames the ks8997 discards frames less than 64 bytes and can be programmed to accept frames up to 1536 bytes. since the ks8997 supports vlan tags, the maximum sizing is adjusted when these tags are present. flow control the ks8997 supports standard 802.3x flow control frames on both transmit and receive sides. on the receive side, if the ks8997 receives a pause control fr ame, the ks8997 will not transmit the next normal frame until the timer, specified in the pause control frame, expires. if another paus e frame is received before the current timer expires, the timer will be updated with the new value in the second pause frame. during this period (being flow controlled), only flow control packets from the ks8997 will be transmitted. on the transm it side, the ks8997 has intelligent and efficient ways to determine when to invo ke flow control. the flow control is based on av ailability of the system resources, including available buffers, availabl e transmit queues and available receive queues. the ks8997 will flow control a port, whic h just received a packet, if the destination port reso urce is being used up. the ks8997 will issue a flow control frame (xoff), cont aining the maximum pause ti me defined in ieee standard 802.3x. once the resource is freed up, the ks8997 will se nd out the other flow control frame (xon) with zero pause time to turn off the flow control (turn on transmission to the port). a hysteres is feature is provided to prevent flow control mechanism from being activated and deactivated too many times. the ks 8997 will flow control all ports if the receive queue becomes full. half-duplex back pressure half duplex back pressure opt ion (note: not in 802.3 standards) is also provided. the activation and deactivation conditions are the same as the above in full-duplex mode. if back pressure is required, the ks8997 will send preambles to defer other stations? tran smission (carrier sense deference). to avoid jabber and excessive deference defined in 802.3 standard, afte r a certain time it will disc ontinue the carrier sense but it will raise the carrier sense quickly. this short silent time (no carrier sense) is to prevent other stations from sending out packets and keeps other stations in carrier sense defe rred state. if the port has packets to send duri ng a back pressure situation, the carrier sense type back pressure will be inte rrupted and those packets will be transm itted instead. if there are no more packets to send, carrier sense type back pressure will be active again until switch resources free up. if a collision occurs, the binary exponential back-off algorithm is skipped and carrier sense is generated immediately, reducing the chance of further colliding and maintaining carri er sense to prevent reception of packets. broadcast storm protection the ks8997 has an intelligent option to protect the switch system from receiving too many broadcast packets. broadcast packet s will be forwarded to all ports exce pt the source port, and thus will use too many sw itch resources (bandwidth and available space in tr ansmit queues). the ks8997 will discard broadcast packets if the number of those packets exceeds the threshold (c onfigured by strapping during reset and eeprom settings) in a preset period of time. if the preset period expires it will then resume receiving br oadcast packets until the th reshold is reached. the options are 5% of network line rate for the maximum br oadcast receiving threshold or unlimited (feature off).
micrel, inc. ks8997/KSZ8997 february 2007 19 m9999-022807-1.1 programmable features priority schemes the ks8997 can determine priority thro ugh three different means at the ingres s point. the first method is a simple per port method, the second is via the 802.1p frame tag and the third is by viewing the dscp (tos) field in the ipv4 header. of course for the priority to be effective, the hi gh and low priority queues must be enabled on the destination port or egress point. per port method general priority can be specified on a per port basis. in this ty pe of priority all traffic from the specified input port is considered high priority in the destination queue. this c an be useful in ip phone applications mixed with other data types of traffic where the ip phone connects to a specific port. the ip phone traffic would be high priority (outbound) to the wide area network. the inbound traffic to the ip phone is all of the same priority to the ip phone. 802.1p method this method works well when used with ports that have mi xed data and media flows. the inbound port examines the priority field in the tag and determines t he high or low priority. priority profiles are setup in the priority classification control in the ?eeprom memory map? section. ipv4 dscp method this is another per frame way of determining outbound pr iority. the dscp (differentiated services code point? rfc#2474) method uses the tos field in the ip header to determine high and low priority on a per code point basis. each fully decoded code point can have either a high or lo w priority. a larger spectrum of priority flows can be defined with this larger code space. more specific to implementation, the mo st significant 6 bits of the tos fiel d are fully decoded in to 64 possibilities, and the singular code that results is compared against the corr esponding bit in the dscp register. if the register bit is a 1, the priority is high and if 0, the priority is low. other priority considerations when setting up the priority scheme, one should consider other available controls to regulat e the traffic. one of these is priority control scheme (register 2 bits 2-3) which cont rols the interleaving of high and low priority frames. options allow from a 2:1 ratio up to a setting that sends all the high priority first. this setting controls all ports globally. another global feature is priority buffe r reserve (register 2 bit 1). if this is set, there is a 6kb (10%) buffer dedicated to high priority traffic, otherwise if clear ed the buffer is shared between all traffic. on an individual port basis there ar e controls that enable ds cp, 802.1p, port based and high/low priority queues. these are contained in registers 4-11 bits 5-3 and 0. it should be noted that there is a special pin that generally enables the 802.1p priority for all ports (pin 60). when this pi n is active (high) all ports will have the 802.1p priority enabled unless specifically disabled by eeprom programming (bit 4 of register s 4-11). default high priority is a value of '100' and above in the vlan tag with low priority being a value of '011' and below.
micrel, inc. ks8997/KSZ8997 february 2007 20 m9999-022807-1.1 the table below briefly summarizes priority features. for more detailed settings see ?eeprom memory map? section. register(s) bit(s) global/port description general 2 3-2 global priority control scheme: transmit buffer high/low interleave control 2 1 global priority buffer reserve: reserves 6 kb of the buffer for high priority traffic 4-11 0 port enable port queue split: splits the transmit queue on the desired port for high and low priority traffic dscp priority 4-11 5 port enable port dsc: looks at dscp field in ip header to decide high or low priority 40-47 7-0 global dscp priority points: fully decoded 64-bit register used to determine priority from dscp field (6 bits) in the ip header 802.1p priority 4-11 4 port enable port 802.1p priority: uses the 802.1p priority tag (3 bits) to determine frame priority 3 7-0 global priority classification: determ ines which tag values have high priority per port priority 4-11 3 port enable port priority: determines which ports have high priority traffic table 1. priority control vlan operation the vlan?s are setup by programming the vlan mask registers in the ?eeprom memory map? section. the perspective of the vlan is from the input port and which out put ports it sees directly th rough the switch. for example if port 1 only participated in a vlan with ports 2 and 8 t hen one would set bits 0 and 6 in register 13 (port 1 vlan mask register). note that different ports can be setup independently. an exampl e of this would be where a router is connected to port 8 and each of the other ports would wo rk autonomously. in this conf iguration ports 1 through 7 would only set the mask for port 8 and port 8 would set the ma sk for ports 1 through 7. in this way the router could see all ports and each of the other individual ports would only communicate with the router. all multicast and broadcast frames adhere to the vlan conf iguration. unicast frame treatment is a function of register 2 bit 0. if this bit is set then unicast frames only see ports within t heir vlan. if this bit is cleared unicast frames can traverse vlan?s. vlan tags can be added or removed on a per port basis. fu rther, there are provisions to specify the tag value to be inserted on a per port basis. the table below briefly summarizes vlan features. for mo re detailed settings see ?eeprom memory map? section. register(s) bit(s) global/port description 4-11 2 port insert vlan tags: if specified, will add vlan tags to frames without existing tags 4-11 1 port strip vlan tags: if specified, will re move vlan tags from frames if they exist 2 0 global vlan enforcement: allows unicast frames to adhere or ignore the vlan configuration 13-20 7-0 port vlan mask registers: allo ws configuration of individual vlan grouping 22-38 7-0 port vlan tag insertion values: specifies the vlan tag to be inserted if enabled (see above) table 2. vlan control
micrel, inc. ks8997/KSZ8997 february 2007 21 m9999-022807-1.1 station mac address (c ontrol frames only) the mac source address can be programmed as used in fl ow control frames. the table below briefly summarizes this progammable feature. register(s) bit(s) global/port description 48-53 7-0 global station mac address: used as source ad dress for mac control frames as used in full-duplex flow control mechanisms. table 3. misc. control eeprom operation the eeprom interface utiliz es 2 pins that provide a clock and a serial data path. as part of the initialization sequence, the ks8997 reads the contents of the eeprom a nd loads the values into the appropriate registers. note that the first two bytes in the eeprom must be ?55? and ?99? respec tively for the loading to occur properly. if these first two values are not correc t, all other data will be ignored. data start and stop conditions are signa led on the data line as a state transition during clock high time. a high to low transition indicates start of data and a low to high transiti on indicates a stop condition. t he actual data that traverses the serial line changes during the clock low time. the ks8997 eeprom interface is compat ible with the atmel at24c01a par t. further timing and data sequences can be found in the atmel at24c01a specification. eeprom memory map address name description default (chip) value 0 7-0 signature byte 1. value = ?55? 0x55 1 7-0 signature byte 2. value = ?99? 0x99 general control register 2 7-4 reserved ? set to zero 0000 2 3-2 priority control scheme (all ports) 00 = transmit all high priority before any low priority 01 = transmit high and low priority at a 10:1 ratio 10 = transmit high and low priority at a 5:1 ratio 11 = transmit high and low priority at a 2:1 ratio 00 2 1 priority buffer reserve for high priority traffic 1 = reserve 6kb of buffer space for high priority 0 = none reserved 0 2 0 vlan enforcement 1 = all unicast frames adhere to vlan configuration 0 = unicast frames ignore vlan configuration 0 priority classification co ntrol ? 802.1p tag field 3 7 1 = state ?111? is high priority 0 = state ?111? is low priority 1 3 6 1 = state ?110? is high priority 0 = state ?110? is low priority 1 3 5 1 = state ?101? is high priority 0 = state ?101? is low priority 1 3 4 1 = state ?100? is high priority 0 = state ?100? is low priority 1 3 3 1 = state ?011? is high priority 0 = state ?011? is low priority 0 3 2 1 = state ?010? is high priority 0 = state ?010? is low priority 0 3 1 1 = state ?001? is high priority 0
micrel, inc. ks8997/KSZ8997 february 2007 22 m9999-022807-1.1 address name description default (chip) value 0 = state ?001? is low priority 3 0 1 = state ?000? is high priority 0 = state ?000? is low priority 0 port 1 control register 4 7-6 reserved ? set to zero 00 4 5 tos priority classification enable for port 1 1 = enable 0 = disable 0 4 4 802.1p priority classification enable for port 1 1 = enable 0 = disable 0 4 3 port based priority classification for port 1 1 = high priority 0 = low priority 0 4 2 insert vlan tags for port 1 if non-existent 1 = enable 0 = disable 0 4 1 strip vlan tags for port 1 if existent 1 = enable 0 = disable 0 4 0 enable high and low output priority queues for port 1 1 = enable 0 = disable 0 port 2 control register 5 7-6 reserved ? set to zero 00 5 5 tos priority classification enable for port 2 1 = enable 0 = disable 0 5 4 802.1p priority classification enable for port 2 1 = enable 0 = disable 0 5 3 port based priority classification for port 2 1 = high priority 0 = low priority 0 5 2 insert vlan tags for port 2 if non-existent 1 = enable 0 = disable 0 5 1 strip vlan tags for port 2 if existent 1 = enable 0 = disable 0 5 0 enable high and low output priority queues for port 2 1 = enable 0 = disable 0 port 3 control register 6 7-6 reserved ? set to zero 00 6 5 tos priority classification enable for port 3 1 = enable 0 = disable 0 6 4 802.1p priority classification enable for port 3 1 = enable 0 = disable 0 6 3 port based priority classification for port 3 1 = high priority 0
micrel, inc. ks8997/KSZ8997 february 2007 23 m9999-022807-1.1 address name description default (chip) value 0 = low priority 6 2 insert vlan tags for port 3 if non-existent 1 = enable 0 = disable 0 6 1 strip vlan tags for port 3 if existent 1 = enable 0 = disable 0 6 0 enable high and low output priority queues for port 3 1 = enable 0 = disable 0 port 4 control register 7 7-6 reserved ? set to zero 00 7 5 tos priority classification enable for port 4 1 = enable 0 = disable 0 7 4 802.1p priority classification enable for port 4 1 = enable 0 = disable 0 7 3 port based priority classification for port 4 1 = high priority 0 = low priority 0 7 2 insert vlan tags for port 4 if non-existent 1 = enable 0 = disable 0 7 1 strip vlan tags for port 4 if existent 1 = enable 0 = disable 0 7 0 enable high and low output priority queues for port 4 1 = enable 0 = disable 0 port 5 control register 8 7-6 reserved ? set to zero 00 8 5 tos priority classification enable for port 5 1 = enable 0 = disable 0 8 4 802.1p priority classification enable for port 5 1 = enable 0 = disable 0 8 3 port based priority classification for port 5 1 = high priority 0 = low priority 0 8 2 insert vlan tags for port 5 if non-existent 1 = enable 0 = disable 0 8 1 strip vlan tags for port 5 if existent 1 = enable 0 = disable 0 8 0 enable high and low output priority queues for port 5 1 = enable 0 = disable 0 port 6 control register 9 7-6 reserved ? set to zero 00
micrel, inc. ks8997/KSZ8997 february 2007 24 m9999-022807-1.1 address name description default (chip) value 9 5 tos priority classification enable for port 6 1 = enable 0 = disable 0 9 4 802.1p priority classification enable for port 6 1 = enable 0 = disable 0 9 3 port based priority classification for port 6 1 = high priority 0 = low priority 0 9 2 insert vlan tags for port 6 if non-existent 1 = enable 0 = disable 0 9 1 strip vlan tags for port 6 if existent 1 = enable 0 = disable 0 9 0 enable high and low output priority queues for port 6 1 = enable 0 = disable 0 port 7 control register 10 7-6 reserved ? set to zero 00 10 5 tos priority classification enable for port 7 1 = enable 0 = disable 0 10 4 802.1p priority classification enable for port 7 1 = enable 0 = disable 0 10 3 port based priority classification for port 7 1 = high priority 0 = low priority 0 10 2 insert vlan tags for port 7 if non-existent 1 = enable 0 = disable 0 10 1 strip vlan tags for port 7 if existent 1 = enable 0 = disable 0 10 0 enable high and low output priority queues for port 7 1 = enable 0 = disable 0 port 8 control register 11 7-6 reserved ? set to zero 00 11 5 tos priority classification enable for port 8 1 = enable 0 = disable 0 11 4 802.1p priority classification enable for port 8 1 = enable 0 = disable 0 11 3 port based priority classification for port 8 1 = high priority 0 = low priority 0 11 2 insert vlan tags for port 8 if non-existent 1 = enable 0 = disable 0 11 1 strip vlan tags for port 8 if existent 1 = enable 0 = disable 0
micrel, inc. ks8997/KSZ8997 february 2007 25 m9999-022807-1.1 address name description default (chip) value 11 0 enable high and low output priority queues for port 8 1 = enable 0 = disable 0 reserved register 12 7-0 reserved 0x00 port 1 vlan mask register 13 7 reserved 1 13 6 port 8 inclusion 1 = port 8 in the same vlan as port 1 0 = port 8 not in the same vlan as port 1 1 13 5 port 7 inclusion 1 = port 7 in the same vlan as port 1 0 = port 7 not in the same vlan as port 1 1 13 4 port 6 inclusion 1 = port 6 in the same vlan as port 1 0 = port 6 not in the same vlan as port 1 1 13 3 port 5 inclusion 1 = port 5 in the same vlan as port 1 0 = port 5 not in the same vlan as port 1 1 13 2 port 4 inclusion 1 = port 4 in the same vlan as port 1 0 = port 4 not in the same vlan as port 1 1 13 1 port 3 inclusion 1 = port 3 in the same vlan as port 1 0 = port 3 not in the same vlan as port 1 1 13 0 port 2 inclusion 1 = port 2 in the same vlan as port 1 0 = port 2 not in the same vlan as port 1 1 port 2 vlan mask register 14 7 reserved 1 14 6 port 8 inclusion 1 = port 8 in the same vlan as port 2 0 = port 8 not in the same vlan as port 2 1 14 5 port 7 inclusion 1 = port 7 in the same vlan as port 2 0 = port 7 not in the same vlan as port 2 1 14 4 port 6 inclusion 1 = port 6 in the same vlan as port 2 0 = port 6 not in the same vlan as port 2 1 14 3 port 5 inclusion 1 = port 5 in the same vlan as port 2 0 = port 5 not in the same vlan as port 2 1 14 2 port 4 inclusion 1 = port 4 in the same vlan as port 2 0 = port 4 not in the same vlan as port 2 1 14 1 port 3 inclusion 1 = port 3 in the same vlan as port 2 0 = port 3 not in the same vlan as port 2 1 14 0 port 2 inclusion 1 = port 2 in the same vlan as port 2 0 = port 2 not in the same vlan as port 2 1
micrel, inc. ks8997/KSZ8997 february 2007 26 m9999-022807-1.1 address name description default (chip) value port 3 vlan mask register 15 7 reserved 1 15 6 port 8 inclusion 1 = port 8 in the same vlan as port 3 0 = port 8 not in the same vlan as port 3 1 15 5 port 7 inclusion 1 = port 7 in the same vlan as port 3 0 = port 7 not in the same vlan as port 3 1 15 4 port 6 inclusion 1 = port 6 in the same vlan as port 3 0 = port 6 not in the same vlan as port 3 1 15 3 port 5 inclusion 1 = port 5 in the same vlan as port 3 0 = port 5 not in the same vlan as port 3 1 15 2 port 4 inclusion 1 = port 4 in the same vlan as port 3 0 = port 4 not in the same vlan as port 3 1 15 1 port 3 inclusion 1 = port 3 in the same vlan as port 3 0 = port 3 not in the same vlan as port 3 1 15 0 port 2 inclusion 1 = port 2 in the same vlan as port 3 0 = port 2 not in the same vlan as port 3 1 port 4 vlan mask register 16 7 reserved 1 16 6 port 8 inclusion 1 = port 8 in the same vlan as port 4 0 = port 8 not in the same vlan as port 4 1 16 5 port 7 inclusion 1 = port 7 in the same vlan as port 4 0 = port 7 not in the same vlan as port 4 1 16 4 port 6 inclusion 1 = port 6 in the same vlan as port 4 0 = port 6 not in the same vlan as port 4 1 16 3 port 5 inclusion 1 = port 5 in the same vlan as port 4 0 = port 5 not in the same vlan as port 4 1 16 2 port 4 inclusion 1 = port 4 in the same vlan as port 4 0 = port 4 not in the same vlan as port 4 1 16 1 port 3 inclusion 1 = port 3 in the same vlan as port 4 0 = port 3 not in the same vlan as port 4 1 16 0 port 2 inclusion 1 = port 2 in the same vlan as port 4 0 = port 2 not in the same vlan as port 4 1 port 5 vlan mask register 17 7 reserved 1 17 6 port 8 inclusion 1 = port 8 in the same vlan as port 5 0 = port 8 not in the same vlan as port 5 1 17 5 port 7 inclusion 1 = port 7 in the same vlan as port 5 0 = port 7 not in the same vlan as port 5 1
micrel, inc. ks8997/KSZ8997 february 2007 27 m9999-022807-1.1 address name description default (chip) value 17 4 port 6 inclusion 1 = port 6 in the same vlan as port 5 0 = port 6 not in the same vlan as port 5 1 17 3 port 5 inclusion 1 = port 5 in the same vlan as port 5 0 = port 5 not in the same vlan as port 5 1 17 2 port 4 inclusion 1 = port 4 in the same vlan as port 5 0 = port 4 not in the same vlan as port 5 1 17 1 port 3 inclusion 1 = port 3 in the same vlan as port 5 0 = port 3 not in the same vlan as port 5 1 17 0 port 2 inclusion 1 = port 2 in the same vlan as port 5 0 = port 2 not in the same vlan as port 5 1 port 6 vlan mask register 18 7 reserved 1 18 6 port 8 inclusion 1 = port 8 in the same vlan as port 6 0 = port 8 not in the same vlan as port 6 1 18 5 port 7 inclusion 1 = port 7 in the same vlan as port 6 0 = port 7 not in the same vlan as port 6 1 18 4 port 6 inclusion 1 = port 6 in the same vlan as port 6 0 = port 6 not in the same vlan as port 6 1 18 3 port 5 inclusion 1 = port 5 in the same vlan as port 6 0 = port 5 not in the same vlan as port 6 1 18 2 port 4 inclusion 1 = port 4 in the same vlan as port 6 0 = port 4 not in the same vlan as port 6 1 18 1 port 3 inclusion 1 = port 3 in the same vlan as port 6 0 = port 3 not in the same vlan as port 6 1 18 0 port 2 inclusion 1 = port 2 in the same vlan as port 6 0 = port 2 not in the same vlan as port 6 1 port 7 vlan mask register 19 7 reserved 1 19 6 port 8 inclusion 1 = port 8 in the same vlan as port 7 0 = port 8 not in the same vlan as port 7 1 19 5 port 7 inclusion 1 = port 7 in the same vlan as port 7 0 = port 7 not in the same vlan as port 7 1 19 4 port 6 inclusion 1 = port 6 in the same vlan as port 7 0 = port 6 not in the same vlan as port 7 1 19 3 port 5 inclusion 1 = port 5 in the same vlan as port 7 0 = port 5 not in the same vlan as port 7 1 19 2 port 4 inclusion 1 = port 4 in the same vlan as port 7 0 = port 4 not in the same vlan as port 7 1
micrel, inc. ks8997/KSZ8997 february 2007 28 m9999-022807-1.1 address name description default (chip) value 19 1 port 3 inclusion 1 = port 3 in the same vlan as port 7 0 = port 3 not in the same vlan as port 7 1 19 0 port 2 inclusion 1 = port 2 in the same vlan as port 7 0 = port 2 not in the same vlan as port 7 1 port & vlan mask register 20 7 reserved 1 20 6 port 8 inclusion 1 = port 8 in the same vlan as port 8 0 = port 8 not in the same vlan as port 8 1 20 5 port 7 inclusion 1 = port 7 in the same vlan as port 8 0 = port 7 not in the same vlan as port 8 1 20 4 port 6 inclusion 1 = port 6 in the same vlan as port 8 0 = port 6 not in the same vlan as port 8 1 20 3 port 5 inclusion 1 = port 5 in the same vlan as port 8 0 = port 5 not in the same vlan as port 8 1 20 2 port 4 inclusion 1 = port 4 in the same vlan as port 8 0 = port 4 not in the same vlan as port 8 1 20 1 port 3 inclusion 1 = port 3 in the same vlan as port 8 0 = port 3 not in the same vlan as port 8 1 20 0 port 2 inclusion 1 = port 2 in the same vlan as port 8 0 = port 2 not in the same vlan as port 8 1 reserved register 21 7-0 reserved 0xff port 1 vlan tag insertion value registers 22 7-5 user priority [2:0] 000 22 4 cfi 0 22 3-0 vid [11:8] 0x0 23 7-0 vid [7:0] 0x00 port 2 vlan tag insertion value registers 24 7-5 user priority [2:0] 000 24 4 cfi 0 24 3-0 vid [11:8] 0x0 25 7-0 vid [7:0] 0x00 port 3 vlan tag insertion value registers 26 7-5 user priority [2:0] 000 26 4 cfi 0 26 3-0 vid [11:8] 0x0 27 7-0 vid [7:0] 0x00
micrel, inc. ks8997/KSZ8997 february 2007 29 m9999-022807-1.1 address name description default (chip) value port 4 vlan tag insertion value registers 28 7-5 user priority [2:0] 000 28 4 cfi 0 28 3-0 vid [11:8] 0x0 29 7-0 vid [7:0] 0x00 port 5 vlan tag insertion value registers 30 7-5 user priority [2:0] 000 30 4 cfi 0 30 3-0 vid [11:8] 0x0 31 7-0 vid [7:0] 0x00 port 6 vlan tag insertion value registers 32 7-5 user priority [2:0] 000 32 4 cfi 0 32 3-0 vid [11:8] 0x0 33 7-0 vid [7:0] 0x00 port 7 vlan tag insertion value registers 34 7-5 user priority [2:0] 000 34 4 cfi 0 34 3-0 vid [11:8] 0x0 35 7-0 vid [7:0] 0x00 port 8 vlan tag insertion value registers 36 7-5 user priority [2:0] 000 36 4 cfi 0 36 3-0 vid [11:8] 0x0 37 7-0 vid [7:0] 0x00 reserved register 38 7-0 reserved 0x00 diff serv code point registers 40 7-0 dscp[63:56] 0x00 41 7-0 dscp[55:48] 0x00 42 7-0 dscp[47:40] 0x00 43 7-0 dscp[39:32] 0x00 44 7-0 dscp[31:24] 0x00 45 7-0 dscp[23:16 0x00 46 7-0 dscp[15:8] 0x00 47 7-0 dscp[7:0] 0x00
micrel, inc. ks8997/KSZ8997 february 2007 30 m9999-022807-1.1 address name description default (chip) value station mac address registers (all ports ? mac control frames only) 48 7-0 mac address [47:40] 0x00 49 7-0 mac address [39:32] 0x40 50 7-0 mac address [31:24] 0x05 51 7-0 mac address [23:16] 0x43 52 7-0 mac address [15:8] 0x5e 53 7-0 mac address [7:0] 0xfe note: the mac address is reset to the value in the above table, but can set to any value via the eeprom interface. this mac address is used as the source address in mac control frames that execute flow control between link peers.
micrel, inc. ks8997/KSZ8997 february 2007 31 m9999-022807-1.1 absolute maximum ratings (1) supply voltage (vdd_rx, vdd_tx, vdd_rcv, vdd, vdd_p lltx).............................. ?0.5v to +2.3v (vddio) ................................................. ?0.5v to +3.8v input voltag e ............................................. ?0.5v to +4.0v output volt age .......................................... ?0.5v to +4.0v lead temperature (sold ering, 10 sec) .................... 270c storage temperature (t s )...................... ?55c to +150c operating ratings (2) supply voltage (vdd_rx, vdd_tx, vdd_rcv, vdd, vdd_pllt x) .......................................+2.0v to +2.3v (vddio) .....................+2.0v to +2 .3v or +3.0v to +3.6v ambient temperature (t a) ........................ ?0c to +70c package thermal resistance (3) pqfp ( ja ) no air fl ow ................................ 42.91c/w electrical characteristics (4) v dd = 2.0v to 2.3v; t a = 0c to +70c; unless noted. symbol parameter condition min typ max units v dd supply voltage 2.00 2.10 2.30 v 100basetx operation 100basetx (total) 0.61 a i dx 100basetx (transmitter) 0.35 a i da 100basetx (analog) 0.18 a i dd 100basetx (digital) 0.08 a 10basetx operation?all ports 100% utilization 10basetx (total) 0.90 a i dx 10basetx (transmitter) 0.72 a i ddc 10basetx (analog) 0.11 a i ddio 10basetx (digital) 0.07 a ttl inputs v ih input high voltage (1/2 v ddio ) +0.4v v v il input low voltage (1/2 v ddio ) ?0.4 v i in input current v in = gnd ~ v dd ?10 10 a ttl outputs v oh output high voltage i oh = ?4ma v ddio ?0.4 v v ol output low voltage i ol = 4ma 0.4 v |i oz | output tri-state leakage 10 a 100basetx transmit (measured differentially after 1:1 transformer) v o peak differential output voltage 50 ? from each output to v dd 0.95 1.05 v v imb output voltage imbalance 50 ? from each output to v dd 2 % rise/fall time 3 5 ns t r , t t rise/fall time imbalance 0 0.5 ns
micrel, inc. ks8997/KSZ8997 february 2007 32 m9999-022807-1.1 symbol parameter condition min typ max units duty cycle distortion 0.5 ns overshoot 5 % v set reference voltage of iset 0.75 v output jitters peak-to-peak 0.7 1.4 ns 10baset receive v sq squelch threshold 5mhz square wave 400 mv 10baset transmit (measured differentially after 1:1 transformer) v ddat = 2.5v v p peak differential output voltage 50 ? from each output to v dd 2.3 v jitters added 50 ? from each output to v dd 3.5 v rise/fall times 28 ns notes: 1. exceeding the absolute maximum rating may damage the device. 2. the device is not guaranteed to function outside its operati ng rating. unused inputs must always be tied to an appropriate logic voltage level (ground to vdd). 3. no hs (heat spreader) in package. 4. specification for packaged product only.
micrel, inc. ks8997/KSZ8997 february 2007 33 m9999-022807-1.1 timing diagrams figure 2. eeprom input timing diagram symbol parameter min typ max units t cyc clock cycle 16384 ns t s set-up time 20 ns t h hold time 20 ns table 4. eeprom timing parameters figure 3. eeprom output timing diagram symbol parameter min typ max units t cyc clock cycle 16384 ns t ov set-up time 4096 4112 4128 ns table 5. eeprom output timing parameters
micrel, inc. ks8997/KSZ8997 february 2007 34 m9999-022807-1.1 reference circuit see ?i/o description? section for pull-up/pull-down and float information. figure 4. unmanaged programming circuit
micrel, inc. ks8997/KSZ8997 february 2007 35 m9999-022807-1.1 4b/5b coding in 100basetx and 100basefx the data and frame control are encoded in the transmitter (and decoded in the receiver) using a 4b/5b code. the extra code space is r equired to encode extra control (frame delineation) points. it is also used to reduce run length as well as supply sufficient transitions for clock recovery. the table below provides the translation for the 4b/5b coding. code type 4b code 5b code value data 0000 11110 data value 0 0001 01001 data value 1 0010 10100 data value 2 0011 10101 data value 3 0100 01010 data value 4 0101 01011 data value 5 0110 01110 data value 6 0111 01111 data value 7 1000 10010 data value 8 1001 10011 data value 9 1010 10110 data value a 1011 10111 data value b 1100 11010 data value c 1101 11011 data value d 1110 11100 data value e 1111 11101 data value f control not defined 11111 idle 0101 11000 start delimiter part 1 0101 10001 start delimiter part 2 not defined 01101 end delimiter part 1 not defined 00111 end delimiter part 2 not defined 00100 transmit error invalid not defined 00000 invalid code not defined 00001 invalid code not defined 00010 invalid code not defined 00011 invalid code not defined 00101 invalid code not defined 00110 invalid code not defined 01000 invalid code not defined 01100 invalid code not defined 10000 invalid code not defined 11001 invalid code table 6. 4b/5b coding
micrel, inc. ks8997/KSZ8997 february 2007 36 m9999-022807-1.1 mlt3 coding for 100basetx operation the nrzi (non-return to zero inve rt on ones) signal is line coded as mlt3. the net result of using mlt3 is to reduce the emi (electro magnetic inte rference) of the signal over twisted pair media. in nrzi coding, the level changes from high to low or low to high for every ?1? bit. for a ?0? bit there is no transition. mlt3 line coding transitions through three distinct levels. for ev ery transition of the nrzi signal the mlt3 signal either increments or decrements depending on the cu rrent state of the signal. for instance if the mlt3 level is at its lowest point the next two nrzi transitions will ch ange the mlt3 signal initially to th e middle level followed by the highest level (second nrzi transition). on the next nrzi change, the mlt3 level w ill decrease to the middle level. on the following transition of the nrzi signal the mlt3 level will move to the lowest level where the cycle repeats. the diagram below describes the level changes. note that in the actual 100basetx circuit t here is a scrambling circuit and that scrambling is not shown in this diagram. figure 5. mlt3 coding mac frame for 802.3 the mac (media access control) fields are described in the table below: field octect length description preamble/sfd 8 preamble and start of frame delimiter da 6 48-bit destination mac address sa 6 48-bit source mac address 802.1p tag 4 vlan and priority tag (optional) length 2 frame length protocol/data 46 to 1500 higher layer protocol and frame data frame crc 4 32-bit cyclical redundancy check esd 1 end of stream delimiter idle variable inter frame idles table 7. mac frame for 802.3
micrel, inc. ks8997/KSZ8997 february 2007 37 m9999-022807-1.1 selection of isolation transformer (1) one simple 1:1 isolation transformer is needed at the line in terface. an isolation transformer with integrated common- mode choke is recommended for exceeding fcc requirements. the following table gives recommended transformer characteristics. characteristics name value test condition turns ratio 1 ct : 1 ct open-circuit inductance (min.) 350h 100mv, 100 khz, 8ma leakage inductance (max.) 0.4h 1mhz (min.) inter-winding capacitance (max.) 12pf d.c. resistance (max.) 0.9 ? insertion loss (max.) 1.0db 0mhz to 65mhz hipot (min.) 1500vrms note: 1. the ieee 802.3u standard for 100basetx assumes a transformer loss of 0.5db. for the transmit line transformer, insertion los s of up to 1.3db can be compensated by increasing the line drive current by means of reducing the iset resistor value. selection of referenc e oscillator/crystal an oscillator or crystal with the followi ng typical characteristics is recommended. characteristics name value test condition frequency 25.00000 mhz maximum frequency tolerance 100 ppm maximum jitter 150 ps(pk-pk) the following transformer vendors provide com patible magnetic parts for micrel?s device: 4-port integrated single-port type vendor part vendor part transformer only pulse h1164 pulse h1102 table 8. qualified magnetics lists
micrel, inc. ks8997/KSZ8997 february 2007 38 m9999-022807-1.1 package information 128-pin pqfp (q)
micrel, inc. ks8997/KSZ8997 february 2007 39 m9999-022807-1.1 micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944-0800 fax +1 (408) 474-1000 web http:/www.micrel.com the information furnished by micrel in this data sheet is belie ved to be accurate and reliable. however, no responsibility is a ssumed by micrel for its use. micrel reserves the right to change circuitry and specificati ons at any time without notification to the customer. micrel products are not designed or authori zed for use as components in life support app liances, devices or systems where malfu nction of a product can reasonably be expected to result in personal injury. li fe support devices or systems are devices or systems that (a ) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to resul t in a significant injury to the user. a purchaser?s use or sale of micrel products for use in life s upport appliances, devices or systems is a pu rchaser?s own risk and purchaser agrees to fully indemnify micrel fo r any damages resulting from such use or sale. ? 2003 micrel, incorporated.

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